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| SL74HCT273 Octal D Flip-Flop with Common Clock and Reset High-Performance Silicon-Gate CMOS The SL74HCT273 is identical in pinout to the LS/ALS273. The SL74HCT273 may be used as a level converter for interfacing TTL or NMOS outputs to High-Speed CMOS inputs. This device consists of eight D flip-flops with common Clock and Reset inputs. Each flip-flop is loaded with a low-to-high transition of the Clock input. Reset is asynchronous and active low. * TTL/NMOS Compatible Input Levels * Outputs Directly Interface to CMOS, NMOS, and TTL * Operating Voltage Range: 4.5 to 5.5 V * Low Input Current: 1.0 A ORDERING INFORMATION SL74HCT273N Plastic SL74HCT273D SOIC TA = -55 to 125 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE PIN 20=VCC PIN 10 = GND Reset L H H H H X = don't care L Inputs Clock X D X H L X X Output Q L H L no change no change SLS System Logic Semiconductor SL74HCT273 MAXIMUM RATINGS * Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 20 35 75 750 500 -65 to +150 260 Unit V V V mA mA mA mW C C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, t f Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) Min 4.5 0 -55 0 Max 5.5 VCC +125 500 Unit V V C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ). CC Unused outputs must be left open. SLS System Logic Semiconductor IN74HCT273 DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Symbol Parameter Test Conditions V Guaranteed Limit 25 C to -55C 2.0 2.0 0.8 0.8 4.4 5.4 3.98 0.1 0.1 0.26 0.1 4.0 85 C 2.0 2.0 0.8 0.8 4.4 5.4 3.84 0.1 0.1 0.33 1.0 40 125 C 2.0 2.0 0.8 0.8 4.4 5.4 3.7 0.1 0.1 0.4 1.0 160 A A V Unit VIH VIL VOH Minimum High-Level Input Voltage Maximum Low -Level Input Voltage Minimum High-Level Output Voltage VOUT=0.1 V or VCC-0.1 V IOUT 20 A VOUT=0.1 V or VCC-0.1 V IOUT 20 A VIN=VIH or VIL IOUT 20 A VIN=VIH or VIL IOUT 4.0 mA 4.5 5.5 4.5 5.5 4.5 5.5 4.5 4.5 5.5 4.5 5.5 5.5 V V V VOL Maximum Low-Level Output Voltage VIN= VIL or VIH IOUT 20 A VIN= VIL or VIH IOUT 4.0 mA IIN ICC Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Additional Quiescent Supply Current VIN=VCC or GND VIN=VCC or GND IOUT=0A VIN=2.4 V, Any One Input VIN=VCC or GND, Other Inputs IOUT=0A ICC -55C 25C to 125C 2.4 mA 5.5 2.9 SLS System Logic Semiconductor SL74HCT273 AC ELECTRICAL CHARACTERISTICS(VCC =5.0 V 10%, CL=50pF,Input t r=t f=6.0 ns) Guaranteed Limit Symbol fmax tPLH, t PHL tPHL tTLH, t THL CIN Parameter Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) Maximum Propagation Delay, Clock to Q (Figures 1 and 4) Maximum Propagation Delay , Reset to Q (Figures 2 and 4) Maximum Output Transition Time, Any Output (Figures 1 and 4) Maximum Input Capacitance Power Dis sipation Capacitance (Per Gate) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC 25 C to -55C 30 25 25 18 10 85C 24 28 28 20 10 125C 20 35 35 22 10 Unit MHz ns ns ns pF Typical @25C,VCC=5.0 V 30 pF TIMING REQUIREMENTS (VCC =5.0 V 10%, CL=50pF,Input t r=t f=6.0 ns) Guaranteed Limit Symbol tSU th trec Parameter Minimum Setup Time, Data to Clock (Figure 3) Minimum Hold Time, Clock to Data (Figure 3) Minimum Recovery Time, Reset Inactive to Clock (Figure 2) Minimum Pulse Width, Clock (Figure 1) Minimum Pulse Width, Reset (Figure 2) Maximum Input Rise and Fall Times (Figure 1) 25 C to -55C 10 3.0 5.0 85C 12 3.0 5.0 125C 15 3.0 5.0 Unit ns ns ns tw tw tr, tf 12 12 500 15 15 500 18 18 500 ns ns ns SLS System Logic Semiconductor IN74HCT273 Figure 1. Switching waveforms Figure 2. Switching waveforms Figure 3. Switching waveforms Figure 4. Test Circuit EXPANDED LOGIC DIAGRAM SLS System Logic Semiconductor |
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